package miggy.cpu.instructions;

import miggy.api.cpu.Size;
import miggy.api.cpu.DecodedInstruction;
import miggy.cpu.DecodedInstructionImpl;
import miggy.api.cpu.InstructionSet;
import miggy.SystemModel;
import miggy.api.cpu.Instruction;
import miggy.cpu.operands.OperandFactory;

/*
//  Miggy - Java Amiga MachineCore
//  Copyright (c) 2008, Tony Headford
//  All rights reserved.
//
//  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
//  following conditions are met:
//
//    o  Redistributions of source code must retain the above copyright notice, this list of conditions and the
//       following disclaimer.
//    o  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
//       following disclaimer in the documentation and/or other materials provided with the distribution.
//    o  Neither the name of the Miggy Project nor the names of its contributors may be used to endorse or promote
//       products derived from this software without specific prior written permission.
//
//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
//  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
//  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
//  SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
//  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// $Revision: 21 $
*/
public class EXG implements Instruction
{
	public final void register(InstructionSet set)
	{

		int base = 0xc140;
		for(int reg = 0; reg < 8; reg++)
		{
			for(int reg2 = 0; reg2 < 8; reg2++)
			{
				for(int flag = 0; flag < 2; flag++)
				{
					set.add(base + (reg << 9) + (flag << 3) + reg2, this);
				}
			}
		}

		base = 0xc188;
		for(int reg = 0; reg < 8; reg++)
		{
			for(int reg2 = 0; reg2 < 8; reg2++)
			{
				set.add(base + (reg << 9) + reg2, this);
			}
		}

	}

	public int execute(int opcode)
	{
		if((opcode & 0x00f8) == 0x0040)
		{
			//Dn/Dn
			int a = SystemModel.CPU.getDataRegister((opcode & 0x0e00) >> 9);
			int b = SystemModel.CPU.getDataRegister(opcode & 0x0007);
			SystemModel.CPU.setDataRegister((opcode & 0x0e00) >> 9, b);
			SystemModel.CPU.setDataRegister(opcode & 0x0007, a);
		}
		else if ((opcode & 0x00f8) == 0x0048)
		{
			// An/An
			int a = SystemModel.CPU.getAddrRegister((opcode & 0x0e00) >> 9);
			int b = SystemModel.CPU.getAddrRegister(opcode & 0x0007);
			SystemModel.CPU.setAddrRegister((opcode & 0x0e00) >> 9, b);
			SystemModel.CPU.setAddrRegister(opcode & 0x0007, a);
		}
		else
		{
			// Dn/An
			int a = SystemModel.CPU.getDataRegister((opcode & 0x0e00) >> 9);
			int b = SystemModel.CPU.getAddrRegister(opcode & 0x0007);
			SystemModel.CPU.setDataRegister((opcode & 0x0e00) >> 9, b);
			SystemModel.CPU.setAddrRegister(opcode & 0x0007, a);
		}

		return 6;
	}

	public DecodedInstruction disassemble(int address, int opcode)
	{
		Size size = Size.Long;
		DecodedInstructionImpl di = new DecodedInstructionImpl("exg", opcode, address, size);

		if((opcode & 0x00f8) == 0x0040)
		{
			//Dn/Dn
			di.setSrc(OperandFactory.dataReg((opcode & 0x0e00) >> 9));
			di.setDst(OperandFactory.dataReg(opcode & 0x0007));
		}
		else if ((opcode & 0x00f8) == 0x0048)
		{
			// An/An
			di.setSrc(OperandFactory.addrReg((opcode & 0x0e00) >> 9));
			di.setDst(OperandFactory.addrReg(opcode & 0x0007));
		}
		else
		{
			// Dn/An
			di.setSrc(OperandFactory.dataReg((opcode & 0x0e00) >> 9));
			di.setDst(OperandFactory.addrReg(opcode & 0x0007));
		}
		return di;
	}
}
